1. Field of the Invention
This invention relates to a semiconductor integrated circuit, in particular, a semiconductor integrated circuit which is designed by a standard cell method and its design method.
2. Description of the Related Art
A plurality of electronic elements, such as a transistor, are formed on a semiconductor substrate of a semiconductor integrated circuit. These electronic elements are connected to each other by a plurality of wires formed in wiring layers which are arranged on the semiconductor substrate. Here, because resistance values of each wiring layer are different, design rules have been established which have given consideration to each resistance values of each wiring layer.
For example, the resistance value of a first wiring layer (below referred to as “M0 layer”) which is the nearest to the semiconductor substrate is high. As a result, the wires of the M0 layer are generally used to connect the electronic elements which are adjacent to each other. For example, they are used to connect an N type MOS transistor (below referred to as “NMOS”) and P type transistor (below referred to as “PMOS”) which form a CMOS. Alternatively, a second wiring layer (below referred to as “M1 layer”) is formed on the M0 layer, and a third wiring layer (below referred to as “M2 layer”) is formed on the second layer and has resistance value lower than that of M0 layer. Therefore, wires of the M2layer are generally used to connect the electronic elements which are in a position separated from each other.
In this way, because there is need to consider a variety of design rules when designing a semiconductor integrated circuit, circuit design is becoming more complex with higher integration of semiconductor integrated circuits. Consequently, a design method called a standard cell method is used in order to shorten time needed for circuit design (for example, patent document 1, Japanese Laid-Open Patent Publication No. H5-347354). In the standard cell method, a transistor layout (cell) which is designed and verified in advance so that it has a specific logic function, is made to be a basic unit, wires for connecting between cells are arranged by using a calculating machine such as a computer.
A cell which is prepared as a basic unit in the standard cell method is called a basic cell. One basic cell has a simple logical function such as a NAND gate. Generally, as wires (internal wires) which connect a plurality of transistors within one basic cell so that the cell has a specific logical function, wires formed in the M0 layer are mainly used. Wires arranged in layers above the M0 layer may also be used in a basic cell when they are needed to avoid wires crossing. Alternatively, in order to connect a basic cell and another basic cell, wires arranged in layers above the M0 layer, specifically, the M1 and M2 layers, are used.
Meanwhile, a memory cell array including a plurality of memory cells which are arranged in a matrix and a peripheral circuit which is arranged on the periphery of this memory cell array are included in a semiconductor integrated circuit such as a semiconductor memory. In recent years, together with the progress of large capacity in semiconductor memories, there is a tendency for the space which is taken up by a memory cell array in a semiconductor integrated circuit to become larger and the region in which a peripheral circuit are arranged (below referred to as “peripheral circuit region”) to become longer and narrower.
Here, wires of the M2 layer which has a low resistance are generally used in order to connect the electronic elements such as transistors which are separated from each other. As a result, wires of the M2 layer are arranged in a longitudinal direction in the long and narrow peripheral circuit region. As a result, if an attempt is made to make the region in which the memory cell array is placed larger, then the width of peripheral circuit region in which the wires formed in the M2 layer must be narrowed. Therefore, it becomes necessary to reduce the number of conductors which are placed in the M2 layer. Alternatively, if an attempt is made not to reduce the number of conductors which are placed in the M2 layer, then it is no longer possible to make the region for memory cell array larger and high integration become difficult.
In addition, because the basic cell is designed and verified in advance and registered in a cell library in the standard cell method, it is possible to automatically arrange wires (in other words, auto-routing) among the cells using a calculation machine. Alternatively, because a circuit which has a larger scale than the basic cell is not registered in the cell library, auto-routing is not available. Therefore, it is not easy to arrange wires among cells when basic cells are mixed with cells each of which has a larger scale than a basic cell, in particular, it is difficult to perform auto-routing by a calculation machine.